The present invention relates to semiconductor assembly technology, and more particularly to flip-chip interconnections between a semiconductor chip and a substrate.
A common task in the manufacture of microelectronic components involves the manufacture of single chip or multi-chip modules having input/output pins which are inserted into a substrate. The input/output pins provide the needed electrical connections to the integrated circuit chip or chips which are subsequently connected to the substrate or carrier. In other presently known manufacturing processes, a chip is soldered directly to a printed circuit board. With either process, solder flux compositions have typically been applied to the pins in order to connect the component to the selected substrate, for instance, the printed circuit board.
As electronic devices become smaller and denser, greater demands are placed on the ability to establish efficient, reliable interconnections from a semiconductor chip to a substrate. There are three well-known methods for interconnecting chips to a substrate. The three methods are (a) face-up wire bonding, (b) face-up tape-automated bonding, and (c) the flip-chip method. Among these three methods, the flip-chip method has frequently been chosen as a preferred method of semiconductor packaging since it allows the interconnection of a high density device having a large number of input and output paths. Specifically, the flip-chip method is often preferred because it provides short conductivity leads from the chip to the substrate, a small device footprint, low inductance, high frequency capabilities, and good noise control.
As shown in FIG. 2, a flip-chip is a semiconductor chip 10 that is mounted onto a substrate 18 with the surface of the chip 10 facing the substrate 18. Although several materials may be used to form an interconnection between the flip-chip 10 and the substrate 18, solder is one of the more commonly employed materials for a flip-chip bump 12. In the solder interconnection process termed xe2x80x9ccontrolled-collapse chip connection (C4)xe2x80x9d, the solder flip-chip bump 12 is deposited on a conductive terminal on the semiconductor chip 10. Then the semiconductor chip 10 is aligned with the substrate 18 so that the solder flip-chip bump 12 is directly over a flip-chip pad 20 of the substrate 18. The flip-chip bump 12 is then tacked to the substrate 18 and reflowed in the presence of flux, creating an electrical and mechanical connection from the chip 10 to the substrate 18 as well as a path for heat dissipation.
Typically, the chip-substrate joining process involves application of flux on the chip 10 and/or the flip-chip pads 20 of the substrate 18. As shown in FIG. 1, flux 16 is sprayed over the entire surface of the semiconductor chip 10 by a jet sprayer 14, including the previously formed flip-chip bumps 12. Then, the chip 10 is aligned to the substrate 18 having flip-chip pads 20 on its surface, which is further facilitated by the flux viscosity and tackiness. The chip-substrate assembly is then subjected to solder reflow in a furnace under nitrogen or forming gas. In the subsequent cooling cycle of the thermal profile for joining, the solder hardens and at the same time the residual flux vapors deposit on the various exposed surfaces. Under the high temperature solder reflow environment, the flux is mostly removed by thermal decomposition to volatile species. However, a small fraction of these thermally activated species undergoes cross-linking reactions, resulting in resinous/carbonaceous byproducts as residue 22 (FIG. 2) on the C4 connections and all of the other surfaces on the chip 10 and the substrate 18 that are exposed to the volatile species during the solder reflow professing. The flux residue 22 must be removed from all critical surfaces prior to further operation, otherwise it can lead to function failure during long term use due to stress corrosion during exposure to temperature and humidity conditions. Further need for removal of flux residue is dictated by the observation that if any residual film of flux residue remains on the substrate or device surface material, it cause detriment to the adhesion of C4 epoxy encapsulant or underfill which is required for enhanced C4 fatigue life and C4 reliability during production on-off cycles.
Therefore, there exists a need for improved and production worthy methodology which removes flux residue from all critical surfaces.
These and other needs are met by the present invention which provides a method for jet printing a flux pattern on a semiconductor chip to selectively deposit flux on the flip-chip bumps to reduce flux residue from all critical areas of a chip surface. The present invention also provides an apparatus for jet printing a flux pattern which selectively deposit flux on the flip-chip bumps to reduce flux residue from all critical areas of a chip surface.
The method in accordance with the present invention includes determining an arrangement pattern of a plurality of flip-chip bumps formed on a surface of a semiconductor chip. A flux pattern, which is substantially identical to the arrangement pattern of the plurality of flip-chip bumps, is jet printed on the surface of the semiconductor chip. In certain embodiment of the present invention, a semiconductor chip is transported to a predetermined location for jet printing the flux pattern on the chip surface.
The apparatus in accordance with the present invention comprises a support for locating a semiconductor chip, which has a plurality of flip-chip bumps arranged on its surface, at a predetermined location for depositing flux, and a jet printing head for printing a flux pattern, which is substantially identical to an arrangement pattern of the plurality of flip-chip bumps on the semiconductor chip. In certain embodiment of the present invention, the apparatus is further equipped with data storage storing an arrangement pattern of the flip-chip bumps.
Hence, flux is selectively deposited on the flip-chip bumps of the semiconductor chip. This has an advantage of reducing flux residue remaining on the surfaces of both chip and substrate, thereby reducing the risk of the device""s functional failure during long term use due to stress corrosion caused by exposure to temperature and humidity, thus achieving enhanced C4 fatigue life and C4 reliability during production on-off cycles. This invention has an advantage of reducing wasted flux randomly sprayed or brushed all over the entire surface of the chip, thereby reducing manufacturing costs.